Author： Gizdarski E.
Publisher： Springer Publishing Company
ISSN： 0923-8174
Source： Journal of Electronic Testing, Vol.16, Iss.4, 2000-08, pp. : 381-387
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
Abstract
Related content
The Coupling Model for Function and Delay Faults
By Yi Joonhwan
Journal of Electronic Testing, Vol. 21, Iss. 6, 2005-12 ,pp. :
Access to resources
Recommend
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
By Li Huawei
Journal of Electronic Testing, Vol. 21, Iss. 2, 2005-04 ,pp. :
Distributed BIST Architecture to Combat Delay Faults
By Savir J.
Journal of Electronic Testing, Vol. 16, Iss. 4, 2000-08 ,pp. :
Clock Faults Induced Min and Max Delay Violations
By Rossi D. Omaña M. Cazeaux J. Metra C. Mak T.
Journal of Electronic Testing, Vol. 30, Iss. 1, 2014-02 ,pp. :