Author: Juan-Chico J.
Publisher: Springer Publishing Company
ISSN: 0925-1030
Source: Analog Integrated Circuits and Signal Processing, Vol.14, Iss.1-2, 1997-09, pp. : 143-157
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
Abstract
Related content
Performance evaluation of the low-voltage CML D-latch topology
By Alioto M. Mita R. Palumbo G.
Integration, the VLSI Journal, Vol. 36, Iss. 4, 2003-11 ,pp. :