A Novel Integrated CMOS Switch Circuit for High Precision Sample-and-Hold Technique

By Li M.F.   Yep S.Y.   Lim Y.C.  

Analog Integrated Circuits and Signal Processing, Vol. 12, Iss. 3, 1997-04 ,pp. : 211-215

Springer Publishing Company

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Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

By Sugimoto Y.   Sekiya M.  

Analog Integrated Circuits and Signal Processing, Vol. 20, Iss. 2, 1999-08 ,pp. : 149-153

Springer Publishing Company

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A high-speed sample-and-hold circuit based on CMOS transmission lines

By Wang Pingshan  

Analog Integrated Circuits and Signal Processing, Vol. 66, Iss. 2, 2011-02 ,pp. : 245-254

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A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

By Sen Yue   Yiqiang Zhao   Ruilong Pang   Yun Sheng  

Journal of Semiconductors, Vol. 35, Iss. 5, 2014-05 ,pp. : 55009-55014

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A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal

By Lee Tsung-Sum   Lu Chi-Chang  

Analog Integrated Circuits and Signal Processing, Vol. 45, Iss. 1, 2005-10 ,pp. : 37-46

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