The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.31, Iss.3, 2002-06, pp. : 209-224

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Engineering Approach to CMOS-Logic Optimization Allowing for Internal Capacitances and On-Chip Interconnections

By Butuzov A. Kristovskii G.

Russian Microelectronics, Vol. 34, Iss. 5, 2005-09 ,pp. : 328-338

MAIK Nauka/Interperiodica

Access to resources Recommend Favorite

CMOS blocks for on-chip RF test

By Ramzan Rashad

Analog Integrated Circuits and Signal Processing, Vol. 49, Iss. 2, 2006-11 ,pp. : 151-160

Springer Publishing Company

Access to resources Recommend Favorite

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

By Hashimoto Y. Yorozu S. Numata H. Koike M. Tanaka M. Tahara S.

Applied Superconductivity, Vol. 6, Iss. 10, 1999-10 ,pp. : 823-828

Elsevier

Access to resources Recommend Favorite

Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

By Zhao Dan

Analog Integrated Circuits and Signal Processing, Vol. 66, Iss. 1, 2011-01 ,pp. : 67-79

Springer Publishing Company

Access to resources Recommend Favorite

A CMOS Imager with On-Chip Temporal Filtering for Motion Pre-Processing

By Gopalan Anand

Analog Integrated Circuits and Signal Processing, Vol. 37, Iss. 3, 2003-01 ,pp. : 243-251

Springer Publishing Company

Access to resources Recommend Favorite