An efficient test generation for multiple fault coverage of two-rail checkers

Author： Pang Joseph C. W.   Wong Mike W. T.   Lee Y. S.  

Publisher： Taylor & Francis Ltd

ISSN： 1362-3060

Source： International Journal of Electronics, Vol.83, Iss.6, 1997-12, pp. : 837-848

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Modeling Fault Coverage of Random Test Patterns

By Cui H.  

Journal of Electronic Testing, Vol. 19, Iss. 3, 2003-06 ,pp. : 271-284

Springer Publishing Company

Access to resources Recommend Favorite

State and Fault Information for Compaction-Based Test Generation

By Giani A.  

Journal of Electronic Testing, Vol. 18, Iss. 1, 2002-02 ,pp. : 63-72

Springer Publishing Company

Access to resources Recommend Favorite

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures

By Favalli M.  

Journal of Electronic Testing, Vol. 18, Iss. 3, 2002-06 ,pp. : 273-283

Springer Publishing Company

Access to resources Recommend Favorite

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage

By Santos M.B.   Gonçalves F.M.   Teixeira I.C.   Teixeira J.P.  

Journal of Electronic Testing, Vol. 18, Iss. 2, 2002-04 ,pp. : 179-187

Springer Publishing Company

Access to resources Recommend Favorite

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

By Liu X.  

Journal of Electronic Testing, Vol. 19, Iss. 4, 2003-08 ,pp. : 437-445

Springer Publishing Company

Access to resources Recommend Favorite