On the speed-up of lock up time in the PLL frequency synthesizer

Author: Sumi Yasuaki   Obote Shigeki   Tsuda Kazutoshi   Syoubu Kouichi   Fukui Yutaka  

Publisher: Taylor & Francis Ltd

ISSN: 1362-3060

Source: International Journal of Electronics, Vol.84, Iss.2, 1998-02, pp. : 123-130

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract