Absorbing boundary conditions for compact modeling of on-chip passive structures

Author： Ioan Daniel Ciuprina Gabriela Radulescu Marius

ISSN： 0332-1649

Source： COMPEL: Int J for Computation and Maths. in Electrical and Electronic Eng., Vol.25, Iss.3, 2006-07, pp. : 652-659

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

On-chip structures for timing measurement and test

By Kinniment D.J. Maevsky O.V. Bystrov A. Russell G. Yakovlev A.V.

Microprocessors and Microsystems, Vol. 27, Iss. 9, 2003-10 ,pp. : 473-483

Elsevier

Access to resources Recommend Favorite

Performance Analysis of On-Chip Communication Structures under Device Variability

International Journal of Embedded and Real-Time Communication Systems (IJERTCS), Vol. 1, Iss. 4, 2010-10 ,pp. : 40-62

IGI Global_journal

Access to resources Recommend Favorite

Toward on-chip datacenters: a perspective on general trends and on-chip particulars

By Kas Miray

The Journal of Supercomputing, Vol. 62, Iss. 1, 2012-10 ,pp. : 214-226

Springer Publishing Company

Access to resources Recommend Favorite

Trends toward on-chip networked microsystems

By Pinkston Timothy Mark Shin Jeonghee

International Journal of High Performance Computing and Networking, Vol. 3, Iss. 1, 2005-09 ,pp. : 3-18

Inderscience Publishers

Access to resources Recommend Favorite

On-chip implementation of multiprocessor networks and switch fabrics

By Ye Terry Tao Micheli Giovanni De

International Journal of Embedded Systems, Vol. 3, Iss. 4, 2009-01 ,pp. : 209-218

Inderscience Publishers

Access to resources Recommend Favorite