Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

Author: Ben Ahmed Akram   Ben Abdallah Abderazek  

Publisher: Springer Publishing Company

ISSN: 0920-8542

Source: The Journal of Supercomputing, Vol.66, Iss.3, 2013-12, pp. : 1507-1532

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract