A 1.0-mW, 71-dB SNDR, fourth-order Σ∆ interface circuit for MEMS microphones

Author： Picolli Luca   Grassi Marco   Fornasari Andrea   Malcovati Piero  

Publisher： Springer Publishing Company

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.66, Iss.2, 2011-02, pp. : 223-233

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