Monte Carlo simulation of double gate MOSFET including multi sub-band description

By Saint-Martin J.   Bournel A.   Aubry-Fortuna V.   Monsef F.   Chassat C.   Dollfus P.  

Journal of Computational Electronics, Vol. 5, Iss. 4, 2006-12 ,pp. : 439-442

Springer Publishing Company

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Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using multi-objective genetic algorithms

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Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 210-215

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Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

By Rana Ashwani  

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 222-228

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Characterization of defect density created by stress in the gate to drain overlap region using GIDL current model in n-channel MOSFET

By Maouhoub N.  

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 141-143

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Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

By Srivastava Viranjay  

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 229-240

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