CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

By Shauly Eitan N.  

Journal of Low Power Electronics and Applications, Vol. 2, Iss. 1, 2012-01 ,pp. : 1-29

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Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

By Zhou Liang   Parameswaran Ravi   Parsan Farhad A.   Smith Scott C.   Di Jia  

Journal of Low Power Electronics and Applications, Vol. 5, Iss. 2, 2015-05 ,pp. : 81-100

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A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

By Beshay Peter   Ryan Joseph F.   Calhoun Benton H.  

Journal of Low Power Electronics and Applications, Vol. 3, Iss. 2, 2013-05 ,pp. : 159-173

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Reconfigurable Threshold Logic Gates using Memristive Devices

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Journal of Low Power Electronics and Applications, Vol. 3, Iss. 2, 2013-05 ,pp. : 174-193

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Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

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