Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

By Stenin V.  

Russian Microelectronics, Vol. 40, Iss. 3, 2011-05 ,pp. : 170-175

MAIK Nauka/Interperiodica

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Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

By Yinhong Luo   Fengqi Zhang   Hongxia Guo   Yao Xiao   Wen Zhao   Lili Ding   Yuanming Wang  

Journal of Semiconductors, Vol. 36, Iss. 11, 2015-11 ,pp. : 114009-114014

IOP Publishing

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High density and low leakage current based SRAM cell using 45 nm technology

By Akashe Shyam  

International Journal of Electronics, Vol. 100, Iss. 4, 2013-04 ,pp. : 536-552

Taylor & Francis Ltd

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Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

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International Journal of Electronics, Vol. 101, Iss. 6, 2014-06 ,pp. : 831-848

Taylor & Francis Ltd

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Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

By Xinhong Hong   Liyang Pan   Wendi Zhang   Dongmei Ji   Dong Wu   Chen Shen   Jun Xu  

Journal of Semiconductors, Vol. 36, Iss. 11, 2015-11 ,pp. : 114003-114007

IOP Publishing

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