Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

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Journal of Semiconductors, Vol. 35, Iss. 9, 2014-09 ,pp. : 94005-94008

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Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

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Journal of Semiconductors, Vol. 35, Iss. 8, 2014-08 ,pp. : 84011-84016

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ESD robustness concern and optimization for high-voltage p-type LDMOS transistor with thin gate oxide used as the output driver

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On the necessary and sufficient conditions for latch-up in sinusoidal oscillators

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Novel 700 V high-voltage SOI LDMOS structure with folded drift region

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