An FPGA implementation for neural networks with the FDFM processor core approach

Author： Ago Yuki Ito Yasuaki Nakano Koji

ISSN： 1744-5760

Source： International Journal of Parallel, Emergent and Distributed Systems, Vol.28, Iss.4, 2013-08, pp. : 308-320

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Efficient FPGA Implementation of Novel Cryptographic Hashing Core

By Michail H. Kakarountas A. Milidonis A. Goutis C.

Computing Letters, Vol. 2, Iss. 1-2, 2006-05 ,pp. : 21-27

VSP

Access to resources Recommend Favorite

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

By Abderazek Ben Yoshinaga Tsutomu Sowa Masahiro

The Journal of Supercomputing, Vol. 38, Iss. 1, 2006-10 ,pp. : 3-15

Springer Publishing Company

Access to resources Recommend Favorite

Multidimensional DSP Core Synthesis for FPGA

By Mcallister J. Woods R. Walke R Reilly D.

Journal of VLSI Signal Processing, Vol. 43, Iss. 2-3, 2006-06 ,pp. : 207-221

Springer Publishing Company

Access to resources Recommend Favorite

FPGA implementation of log-polar mapping

By Wong Wai Kit Choo Chee Wee Loo Chu Kiong Teh Joo Peng

International Journal of Computer Applications in Technology, Vol. 39, Iss. 1-3, 2010-08 ,pp. : 12-18

Inderscience Publishers

Access to resources Recommend Favorite

Low-resource hardware implementation of the hyperbolic tangent for artificial neural networks

By Baptista Darío Morgado-Dias Fernando

Neural Computing & Applications, Vol. 23, Iss. 3-4, 2013-09 ,pp. : 601-607

Springer Publishing Company

Access to resources Recommend Favorite