Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

ISSN： 1569-8025

Source： Journal of Computational Electronics, Vol.10, Iss.1-2, 2011-06, pp. : 222-228

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Characterization of defect density created by stress in the gate to drain overlap region using GIDL current model in n-channel MOSFET

By Maouhoub N.

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 141-143

Springer Publishing Company

Access to resources Recommend Favorite

Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using multi-objective genetic algorithms

By Bendib T.

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 210-215

Springer Publishing Company

Access to resources Recommend Favorite

DSMC versus WENO-BTE: A double gate MOSFET example

By Cáceres Maria Carrillo José Gamba Irene Majorana Armando Shu Chi-Wang

Journal of Computational Electronics, Vol. 5, Iss. 4, 2006-12 ,pp. : 471-474

Springer Publishing Company

Access to resources Recommend Favorite

Monte Carlo simulation of double gate MOSFET including multi sub-band description

By Saint-Martin J. Bournel A. Aubry-Fortuna V. Monsef F. Chassat C. Dollfus P.

Journal of Computational Electronics, Vol. 5, Iss. 4, 2006-12 ,pp. : 439-442

Springer Publishing Company

Access to resources Recommend Favorite

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

By Abdi M.

Journal of Computational Electronics, Vol. 10, Iss. 1-2, 2011-06 ,pp. : 179-185

Springer Publishing Company

Access to resources Recommend Favorite