A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism

By Ramachandran S.   Srinivasan S.  

VLSI Design, Vol. 15, Iss. 2, 2002-01 ,pp. : 521-528

Taylor & Francis Ltd

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Scoped, coarse-grain memory management and the RTSJ scoped memory model in the development of real-time applications

By Borg Andrew   Wellings Andy  

International Journal of Embedded Systems, Vol. 2, Iss. 3-4, 2007-08 ,pp. : 166-183

Inderscience Publishers

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Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures

By Lee Jong Eun   Choi Kiyoung   Dutt Nikil  

International Journal of Embedded Systems, Vol. 3, Iss. 3, 2008-09 ,pp. : 119-127

Inderscience Publishers

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Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

By Hong Sangjin   Chin Shu-Shin  

Journal of VLSI Signal Processing, Vol. 40, Iss. 2, 2005-06 ,pp. : 239-259

Springer Publishing Company

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Visibility Computation on Reconfigurable Meshes

By Fujimura K.  

Graphical Models and Image Processing, Vol. 59, Iss. 6, 1997-11 ,pp. : 395-406

Academic Press

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