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Journal of Electronic Testing, Vol. 21, Iss. 1, 2005-02 ,pp. : 43-55

Springer Publishing Company

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An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

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Path delay fault testing of multiplexer-based shifters

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Application-Specific Bridging Fault Testing of FPGAs

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Scalable Delay Fault BIST for Use with Low-Cost ATE

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