Reducing average and peak temperatures of VLSI CMOS circuits by means of evolutionary algorithm applied to high level synthesis

Author： Koziel S.   Szczesniak W.  

Publisher： Elsevier

ISSN： 0026-2692

Source： Microelectronics, Vol.34, Iss.12, 2003-12, pp. : 1167-1174

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

By Bisdounis L.   Gouvetas D.   Koufopavlou O.  

International Journal of Electronics, Vol. 84, Iss. 6, 1998-06 ,pp. : 599-613

Taylor & Francis Ltd

Access to resources Recommend Favorite

High Performance CMOS Analog Arithmetic Circuits

By Xu J.  

Analog Integrated Circuits and Signal Processing, Vol. 20, Iss. 3, 1999-09 ,pp. : 193-201

Springer Publishing Company

Access to resources Recommend Favorite

Reducing Average and Peak Test Power Through Scan Chain Modification

By Sinanoglu O.  

Journal of Electronic Testing, Vol. 19, Iss. 4, 2003-08 ,pp. : 457-467

Springer Publishing Company

Access to resources Recommend Favorite

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

By Conti M.  

Analog Integrated Circuits and Signal Processing, Vol. 37, Iss. 2, 2003-11 ,pp. : 85-102

Springer Publishing Company

Access to resources Recommend Favorite

Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology

By Kirgizova A.   Nikiforov A.   Grigor’ev N.   Poljakov I.   Skorobogatov P.  

Russian Microelectronics, Vol. 35, Iss. 3, 2006-05 ,pp. : 162-176

MAIK Nauka/Interperiodica

Access to resources Recommend Favorite