A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

Author: Sen Yue   Yiqiang Zhao   Ruilong Pang   Yun Sheng  

Publisher: IOP Publishing

ISSN: 1674-4926

Source: Journal of Semiconductors, Vol.35, Iss.5, 2014-05, pp. : 55009-55014

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