Simulations of Sub-100 nm Strained Si MOSFETs with High-κ Gate Stacks

By Yang L.   Watling J.   Adamu-Lema F.   Asenov A.   Barker J.  

Journal of Computational Electronics, Vol. 3, Iss. 3-4, 2004-10 ,pp. : 171-175

Springer Publishing Company

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Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

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Journal of Computational Electronics, Vol. 3, Iss. 3-4, 2004-10 ,pp. : 247-250

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Intrinsic Parameter Fluctuations in Conventional MOSFETs at the Scaling Limit: A Statistical Study

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Journal of Computational Electronics, Vol. 3, Iss. 3-4, 2004-10 ,pp. : 203-206

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A simulation framework for modeling charge transport and degradation in high-k stacks

By Larcher Luca   Padovani Andrea   Vandelli Luca  

Journal of Computational Electronics, Vol. 12, Iss. 4, 2013-12 ,pp. : 658-665

Springer Publishing Company

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Analysis of Gate Dielectric Stacks Using the Transmitting Boundary Method: Special Issue on the Proceedings of the INTERNATIONAL WORKSHOP ON COMPUTATIONAL ELECTRONICS (IWCE-9)

By Gehring A.   Kosina H.   Selberherr S.  

Journal of Computational Electronics, Vol. 2, Iss. 2-4, 2003-12 ,pp. : 219-223

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