Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

By Moorthi S.  

International Journal of Electronics, Vol. 96, Iss. 11, 2009-11 ,pp. : 1183-1189

Taylor & Francis Ltd

Access to resources Recommend Favorite

A clock generator for a high-speed high-resolution pipelined A/D converter

By Lei Zhao   Yintang Yang   Zhangming Zhu   Lianxi Liu  

Journal of Semiconductors, Vol. 34, Iss. 2, 2013-02 ,pp. : 25003-25008

IOP Publishing

Access to resources Recommend Favorite

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

By Rantala Arto   Martins David   Åberg Markku  

Analog Integrated Circuits and Signal Processing, Vol. 50, Iss. 1, 2007-01 ,pp. : 69-79

Springer Publishing Company

Access to resources Recommend Favorite

A low jitter PLL clock used for phase change memory

By Xiao Hong   Houpeng Chen   Zhitang Song   Daolin Cai   Xi Li  

Journal of Semiconductors, Vol. 34, Iss. 2, 2013-02 ,pp. : 25012-25016

IOP Publishing

Access to resources Recommend Favorite

A second-order extension of the edge-selection algorithm for a ΣΔ-DAC architecture insensitive to oversampling clock jitter

By Lee Eel-Wan  

International Journal of Electronics, Vol. 88, Iss. 6, 2001-06 ,pp. : 677-693

Taylor & Francis Ltd

Access to resources Recommend Favorite