Modelling of Hfe avalanche degradation in gate controlled bipolar transistors

Publisher： Edp Sciences

E-ISSN： 0035-1687|13|12|597-601

ISSN： 0035-1687

Source： Revue de Physique Appliquée (Paris), Vol.13, Iss.12, 1978-12, pp. : 597-601

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Related content

COMPARISON OF ECL GATE PERFORMANCES USING DIFFERENT HETEROJUNCTION BIPOLAR TRANSISTORS PROCESS

By  

Le Journal de Physique Colloques, Vol. 49, Iss. C4, 1988-09 ,pp. : C4-575-C4-578

Edp Sciences

Access to resources Recommend Favorite

Effects of DC gate and drain bias stresses on the degradation of excimer laser crystallized polysilicon thin film transistors

By  

Journal of Physics: Conference Series , Vol. 10, Iss. 1, 2005-01 ,pp. : 45-48

IOP Publishing

Access to resources Recommend Favorite

Production of square pulses by means of transistors in the avalanche mode.

By  

Journal de Physique Appliqué, Vol. 23, Iss. S3, 1962-03 ,pp. : 40-42

Edp Sciences

Access to resources Recommend Favorite

Fast coincidence circuits using transistors in the avalanche region.

By  

Journal de Physique Appliqué, Vol. 22, Iss. S2, 1961-02 ,pp. : 53-58

Edp Sciences

Access to resources Recommend Favorite

SELECTIVE EPITAXY BASE FOR BIPOLAR TRANSISTORS

By  

Le Journal de Physique Colloques, Vol. 49, Iss. C4, 1988-09 ,pp. : C4-367-C4-370

Edp Sciences

Access to resources Recommend Favorite