Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM V_MIN

By Boley James   Wang Jiajing   Calhoun Benton H.  

Journal of Low Power Electronics and Applications, Vol. 2, Iss. 2, 2012-04 ,pp. : 143-154

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Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits †

By Chairat Soundous   Beigne Edith   Miro-Panades Ivan   Belleville Marc  

Journal of Low Power Electronics and Applications, Vol. 7, Iss. 2, 2017-05 ,pp. : 11-11

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Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

By Lu Chien-Yu   Chuang Ching-Te  

Journal of Low Power Electronics and Applications, Vol. 2, Iss. 4, 2012-12 ,pp. : 282-300

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Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

By Bol David  

Journal of Low Power Electronics and Applications, Vol. 1, Iss. 1, 2011-01 ,pp. : 1-19

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Exploration of Sub-V_T and Near-V_T 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

By Meinerzhagen Pascal   Teman Adam   Giterman Robert   Burg Andreas   Fish Alexander  

Journal of Low Power Electronics and Applications, Vol. 3, Iss. 2, 2013-04 ,pp. : 54-72

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