Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process

Publisher： IOP Publishing

E-ISSN： 1361-6641|30|1|15023-15031

ISSN： 0268-1242

Source： Semiconductor Science and Technology, Vol.30, Iss.1, 2015-01, pp. : 15023-15031

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