Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

By Kim J. B.  

International Journal of Electronics, Vol. 94, Iss. 10, 2007-10 ,pp. : 905-913

Taylor & Francis Ltd

Access to resources Recommend Favorite

Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing

By Nakai T.  

Analog Integrated Circuits and Signal Processing, Vol. 21, Iss. 2, 1999-11 ,pp. : 173-191

Springer Publishing Company

Access to resources Recommend Favorite

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

By Pacha C.  

Analog Integrated Circuits and Signal Processing, Vol. 25, Iss. 1, 2000-10 ,pp. : 7-25

Springer Publishing Company

Access to resources Recommend Favorite

强度解调的光纤光栅振动检测硬件电路设计及实验研究Fiber Bragg Grating Vibration Sensing Hardware Circuit Design and Experiment Research Based on Intensity Demodulation

By 陈树芳   张法业   姜明顺   隋青美   贾磊  

Optoelectronics, Vol. 4, Iss. 2, 2014-06 ,pp. : 13-19

汉斯出版社

Access to resources Recommend Favorite

QMOS digital logic circuit design

By Koshy Kamal J.   Balsara Poras T.  

International Journal of Electronics, Vol. 87, Iss. 5, 2000-05 ,pp. : 531-545

Taylor & Francis Ltd

Access to resources Recommend Favorite