Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

ISSN： 0925-1030

Source： Analog Integrated Circuits and Signal Processing, Vol.25, Iss.1, 2000-10, pp. : 7-25

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

By Kim J. B.

International Journal of Electronics, Vol. 94, Iss. 10, 2007-10 ,pp. : 905-913

Taylor & Francis Ltd

Access to resources Recommend Favorite

Application of advanced metal-oxide-semiconductor transistor in next generation, silicon resonant tunneling MOS transistor, to new logic circuit

By Matsuo N. Kihara H. Takami Y.

Solid-State Electronics, Vol. 47, Iss. 11, 2003-11 ,pp. : 1969-1972

Elsevier

Access to resources Recommend Favorite

Methodology for the design of a 4-bit soft-hardware-logic circuit based on neuron MOS transistors

By Reyes-Barranca M. A. Medina-Santiago A.

International Journal of Electronics, Vol. 95, Iss. 6, 2008-01 ,pp. : 517-530

Taylor & Francis Ltd

Access to resources Recommend Favorite

QMOS digital logic circuit design

By Koshy Kamal J. Balsara Poras T.

International Journal of Electronics, Vol. 87, Iss. 5, 2000-05 ,pp. : 531-545

Taylor & Francis Ltd

Access to resources Recommend Favorite

Design and control of an LCL series parallel resonant converters using bacterial foraging optimisation

By Bayoumi Ehab H.E.

International Journal of Power Electronics, Vol. 4, Iss. 5, 2012-01 ,pp. : 479-504

Inderscience Publishers

Access to resources Recommend Favorite