Negative gate-overlap in nanoscaled DG-MOSFETs with asymmetric gate bias

Author: Shao Xue   Yu Zhiping  

Publisher: Springer Publishing Company

ISSN: 1569-8025

Source: Journal of Computational Electronics, Vol.5, Iss.4, 2006-12, pp. : 389-392

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Related content