Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

Author: Jia Zhang   Haigang Yang   Jiabin Sun   Le Yu   Yuanfeng Wei  

Publisher: IOP Publishing

ISSN: 1674-4926

Source: Journal of Semiconductors, Vol.35, Iss.8, 2014-08, pp. : 85001-85007

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Related content