Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

By Bol David  

Journal of Low Power Electronics and Applications, Vol. 1, Iss. 1, 2011-01 ,pp. : 1-19

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A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention †

By Hiienkari Markus   Teittinen Jukka   Koskinen Lauri   Turnquist Matthew   Mäkipää Jani   Rantala Arto   Sopanen Matti   Kaltiokallio Mikko  

Journal of Low Power Electronics and Applications, Vol. 5, Iss. 2, 2015-04 ,pp. : 57-68

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CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

By Muñoz-Gamarra Jose Luis   Uranga Arantxa   Barniol Nuria  

Micromachines, Vol. 7, Iss. 2, 2016-02 ,pp. : 30-30

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Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review ^†

By Crop Joseph   Krimer Evgeni   Moezzi-Madani Nariman   Pawlowski Robert   Ruggeri Thomas   Chiang Patrick   Erez Mattan  

Journal of Low Power Electronics and Applications, Vol. 1, Iss. 3, 2011-10 ,pp. : 334-356

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The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

By Naeini Mahshid Mojtabavi   Dass Sreedharan Baskara   Ooi Chia Yee  

Journal of Low Power Electronics and Applications, Vol. 7, Iss. 2, 2017-04 ,pp. : 7-7

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