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Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology ^†

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The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

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Journal of Low Power Electronics and Applications, Vol. 7, Iss. 2, 2017-04 ,pp. : 7-7

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CMOS MEMS Fabrication Technologies and Devices

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Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

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