Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation

By Hu Man-Chun   Jang Sheng-Lyang  

International Journal of Electronics, Vol. 84, Iss. 3, 1998-03 ,pp. : 167-185

Taylor & Francis Ltd

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Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially depleted SOI devices

By Chuang C. T.   Lu P. F.   Anderson C. J.  

International Journal of Electronics, Vol. 86, Iss. 1, 1999-01 ,pp. : 55-66

Taylor & Francis Ltd

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Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

By Imam M.A.   Osman M.A.   Osman A.A.  

Microelectronics Reliability, Vol. 44, Iss. 1, 2004-01 ,pp. : 53-63

Elsevier

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Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

By Flandre D.  

Analog Integrated Circuits and Signal Processing, Vol. 21, Iss. 3, 1999-12 ,pp. : 213-228

Springer Publishing Company

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An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

By Gharabagi Roobik  

International Journal of Electronics, Vol. 87, Iss. 2, 2000-02 ,pp. : 129-136

Taylor & Francis Ltd

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