Technology for integrated circuit micropackages for neural interfaces, based on gold–silicon wafer bonding

Author： Saeidi N Schuettler M Demosthenous A Donaldson N

ISSN： 0960-1317

Source： Journal of Micromechanics and Microengineering, Vol.23, Iss.7, 2013-07, pp. : 75021-75032

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Abstract

Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au–Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal–oxide–semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.