Author： Sekar K.
Publisher： Springer Publishing Company
ISSN： 0923-8174
Source： Journal of Electronic Testing, Vol.19, Iss.2, 2003-04, pp. : 113-123
Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.
Abstract
Related content
Access to resources
Recommend
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing, Vol. 22, Iss. 1, 2006-02 ,pp. :
Scalable Delay Fault BIST for Use with Low-Cost ATE
By Polian Ilia
Journal of Electronic Testing, Vol. 20, Iss. 2, 2004-04 ,pp. :
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
By Azaïs F.
Journal of Electronic Testing, Vol. 17, Iss. 2, 2001-04 ,pp. :