An effective logic BIST scheme based on LFSR-reseeding and TVAC

Author：        

Publisher： Taylor & Francis Ltd

ISSN： 1362-3060

Source： International Journal of Electronics, Vol.101, Iss.9, 2014-09, pp. : 1217-1229

Disclaimer: Any content in publications that violate the sovereignty, the constitution or regulations of the PRC is not accepted or approved by CNPIEC.

Previous Menu Next

Related content

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

By Kalligeros E.  

Journal of Electronic Testing, Vol. 18, Iss. 3, 2002-06 ,pp. : 315-332

Springer Publishing Company

Access to resources Recommend Favorite

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

By Kranitis N.  

Journal of Electronic Testing, Vol. 17, Iss. 2, 2001-04 ,pp. : 97-107

Springer Publishing Company

Access to resources Recommend Favorite

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

By Sekar K.  

Journal of Electronic Testing, Vol. 19, Iss. 2, 2003-04 ,pp. : 113-123

Springer Publishing Company

Access to resources Recommend Favorite

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping

By Zhou Bin  

Journal of Electronic Testing, Vol. 27, Iss. 1, 2011-02 ,pp. : 43-56

Springer Publishing Company

Access to resources Recommend Favorite

A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area

By Sikdar Biplab  

Journal of Electronic Testing, Vol. 21, Iss. 1, 2005-02 ,pp. : 83-93

Springer Publishing Company

Access to resources Recommend Favorite