Author： Hwang W. Chuang C. T. Curran B. W. Rosenfield M. G.
Publisher： Taylor & Francis Ltd
ISSN： 1362-3060
Source： International Journal of Electronics, Vol.89, Iss.4, 2002-04, pp. : 267-275
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Abstract
'Tapered gate' is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study of the performance leverage of tapered gate in a partially depleted silicon-on-insulator (PD/SOI) technology. It is shown that the reduced junction capacitance in a PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective. The effects are also shown to be more pronounced for low-VT cases. The study demonstrates that tapered gate remains a viable device sizing technique/methodology for improving performance in a PD/SOI technology.
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