Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits

Author： Stojcev M.K.   Djordjevic G.L.   Stankovic T.R.  

Publisher： Elsevier

ISSN： 0026-2714

Source： Microelectronics Reliability, Vol.44, Iss.1, 2004-01, pp. : 173-178

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